Singulation of microelectronic components with direct bonding interfaces

ABSTRACT

Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

BACKGROUND

An integrated circuit (IC) package typically includes a die wirebonded or soldered to a package substrate. In use, electrical signals and power are passed between the package substrate and the die through the wirebonds or solder.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.

FIG. 1 is a side, cross-sectional view of an example microelectronic assembly including direct bonding, in accordance with various embodiments.

FIG. 2 is a side, cross-sectional exploded view of a portion of the microelectronic assembly of FIG. 1, in accordance with various embodiments.

FIGS. 3 and 4 are side, cross-sectional views of example direct bonding interfaces of a microelectronic component, in accordance with various embodiments.

FIGS. 5-8 are top views of example direct bonding interfaces of a microelectronic component, in accordance with various embodiments.

FIGS. 9-12 are side, cross-sectional views of example direct bonding interfaces of a microelectronic component, in accordance with various embodiments.

FIG. 13 is a side, cross-sectional view of an example microelectronic assembly including direct bonding, in accordance with various embodiments.

FIGS. 14-17 are side, cross-sectional views of example stages in the manufacture of a portion of the microelectronic assembly of FIGS. 1 and 2, in accordance with various embodiments.

FIGS. 18-20, 21A-21B, and 22-23 are side, cross-sectional views of example microelectronic assemblies including direct bonding, in accordance with various embodiments.

FIGS. 24A-24B are various views of a microelectronic assembly including a microelectronic component having a direct bonding interface and a peripheral trench, in accordance with various embodiments.

FIGS. 25-28 are side, cross-sectional views of example microelectronic components having a direct bonding interface and a peripheral trench, in accordance with various embodiments.

FIGS. 29-31 are side, cross-sectional views of example stages in the manufacture of a microelectronic component having a direct bonding interface and a peripheral trench, in accordance with various embodiments.

FIGS. 32A-32C and 33A-33B are side, cross-sectional views of example microelectronic components having a direct bonding interface and a peripheral trench, in accordance with various embodiments.

FIG. 34 is a bottom view of an example microelectronic component having a direct bonding interface and a peripheral trench, in accordance with various embodiments.

FIG. 35 is a top view of a wafer and dies that may be included in a microelectronic component in accordance with any of the embodiments disclosed herein.

FIG. 36 is a side, cross-sectional view of an integrated circuit (IC) device that may be included in a microelectronic component in accordance with any of the embodiments disclosed herein.

FIG. 37 is a side, cross-sectional view of an IC device assembly that may include a microelectronic assembly in accordance with any of the embodiments disclosed herein.

FIG. 38 is a block diagram of an example electrical device that may include a microelectronic assembly in accordance with any of the embodiments disclosed herein.

DETAILED DESCRIPTION

Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrases “A, B, and/or C” and “A, B, or C” mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. The terms “top,” “bottom,” etc. may be used herein to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “a dielectric material” may include one or more dielectric materials. As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). For ease of discussion, the drawings of FIGS. 21A and 21B may be referred to herein as “FIG. 21,” and the drawings of FIGS. 24A and 24B may be referred to herein as “FIG. 24.”

FIG. 1 is a side, cross-sectional view of a microelectronic assembly 100, in accordance with various embodiments. A number of elements are illustrated in FIG. 1 as included in the microelectronic assembly 100, but a number of these elements may not be present in a microelectronic assembly 100. For example, in various embodiments, the heat transfer structure 152, the thermal interface material (TIM) 154, the mold material 126, the microelectronic component 102-2, the underfill material 138, and/or the support component 182 may not be included. Further, FIG. 1 illustrates a number of elements that are omitted from subsequent drawings for ease of illustration, but may be included in any of the microelectronic assemblies 100 disclosed herein. Examples of such elements include the heat transfer structure 152, the TIM 154, the mold material 126, the microelectronic component 102-2, the underfill material 138, and/or the support component 182. Many of the elements of the microelectronic assembly 100 of FIG. 1 are included in other ones of the accompanying drawings; the discussion of these elements is not repeated when discussing these drawings, and any of these elements may take any of the forms disclosed herein. In some embodiments, individual ones of the microelectronic assemblies 100 disclosed herein may serve as a system-in-package (SiP) in which multiple microelectronic components 102 having different functionality are included. In such embodiments, the microelectronic assembly 100 may be referred to as an SiP.

The microelectronic assembly 100 may include an interposer 150 coupled to a microelectronic component 102-1 by a direct bonding (DB) region 130-1. In particular, as illustrated in FIG. 2, the DB region 130-1 may include a DB interface 180-1A at the top surface of the interposer 150, with the DB interface 180-1A including a set of conductive DB contacts 110 and a DB dielectric 108 around the DB contacts 110 of the DB interface 180-1A. The DB region 130-1 may also include a DB interface 180-1B at the bottom surface of the microelectronic component 102-1, with the DB interface 180-1B including a set of DB contacts 110 and a DB dielectric 108 around the DB contacts 110 of the DB interface 180-1B. The DB contacts 110 of the DB interface 180-1A of the interposer 150 may align with the DB contacts 110 of the DB interface 180-1B of the microelectronic component 102-1 so that, in the microelectronic assembly 100, the DB contacts 110 of the microelectronic component 102-1 are in contact with the DB contacts 110 of the interposer 150. In the microelectronic assembly 100 of FIG. 1, the DB interface 180-1A of the interposer 150 may be bonded (e.g., electrically and mechanically) with the DB interface 180-1B of the microelectronic component 102-1 to form the DB region 130-1 coupling the interposer 150 and the microelectronic component 102-1, as discussed further below. More generally, the DB regions 130 disclosed herein may include two complementary DB interfaces 180 bonded together; for ease of illustration, many of the subsequent drawings may omit the identification of the DB interfaces 180 to improve the clarity of the drawings.

As used herein, the term “direct bonding” is used to include metal-to-metal bonding techniques (e.g., copper-to-copper bonding, or other techniques in which the DB contacts 110 of opposing DB interfaces 180 are brought into contact first, then subject to heat and compression) and hybrid bonding techniques (e.g., techniques in which the DB dielectric 108 of opposing DB interfaces 180 are brought into contact first, then subject to heat and sometimes compression, or techniques in which the DB contacts 110 and the DB dielectric 108 of opposing DB interfaces 180 are brought into contact substantially simultaneously, then subject to heat and compression). In such techniques, the DB contacts 110 and the DB dielectric 108 at one DB interface 180 are brought into contact with the DB contacts 110 and the DB dielectric 108 at another DB interface 180, respectively, and elevated pressures and/or temperatures may be applied to cause the contacting DB contacts 110 and/or the contacting DB dielectrics 108 to bond. In some embodiments, this bond may be achieved without the use of intervening solder or an anisotropic conductive material, while in some other embodiments, a thin cap of solder may be used in a DB interconnect to accommodate planarity, and this solder may become an intermetallic compound (IMC) in the DB region 130 during processing. DB interconnects may be capable of reliably conducting a higher current than other types of interconnects; for example, some conventional solder interconnects may form large volumes of brittle IMGs when current flows, and the maximum current provided through such interconnects may be constrained to mitigate mechanical failure.

A DB dielectric 108 may include one or more dielectric materials, such as one or more inorganic dielectric materials. For example, a DB dielectric 108 may include silicon and nitrogen (e.g., in the form of silicon nitride); silicon and oxygen (e.g., in the form of silicon oxide); silicon, carbon, and nitrogen (e.g., in the form of silicon carbonitride); carbon and oxygen (e.g., in the form of a carbon-doped oxide); silicon, oxygen, and nitrogen (e.g., in the form of silicon oxynitride); aluminum and oxygen (e.g., in the form of aluminum oxide); titanium and oxygen (e.g., in the form of titanium oxide); hafnium and oxygen (e.g., in the form of hafnium oxide); silicon, oxygen, carbon, and hydrogen (e.g., in the form of tetraethyl orthosilicate (TEOS)); zirconium and oxygen (e.g., in the form of zirconium oxide); niobium and oxygen (e.g., in the form of niobium oxide); tantalum and oxygen (e.g., in the form of tantalum oxide); and combinations thereof. Some particular embodiments of arrangements of DB dielectrics 108 including multiple dielectric materials are discussed below with reference to FIG. 4.

A DB contact 110 may include a pillar, a pad, or other structure. The DB contacts 110, although depicted in the accompanying drawings in the same manner at both DB interfaces 180 of a DB region 130, may have a same structure at both DB interfaces 180, or the DB contacts 110 at different DB interfaces 180 may have different structures. For example, in some embodiments, a DB contact 110 in one DB interface 180 may include a metal pillar (e.g., a copper pillar), and a complementary DB contact 110 in a complementary DB interface 180 may include a metal pad (e.g., a copper pad) recessed in a dielectric. A DB contact 110 may include any one or more conductive materials, such as copper, manganese, titanium, gold, silver, palladium, nickel, copper and aluminum (e.g., in the form of a copper aluminum alloy), tantalum (e.g., tantalum metal, or tantalum and nitrogen in the form of tantalum nitride), cobalt, cobalt and iron (e.g., in the form of a cobalt iron alloy), or any alloys of any of the foregoing (e.g., copper, manganese, and nickel in the form of manganin). Some particular arrangements of multiple materials in a DB contact 110 are discussed below with reference to FIG. 3). In some embodiments, the DB dielectric 108 and the DB contacts 110 of a DB interface 180 may be manufactured using low-temperature deposition techniques (e.g., techniques in which deposition occurs at temperatures below 250 degrees Celsius, or below 200 degrees Celsius), such as low-temperature plasma-enhanced chemical vapor deposition (PECVD).

FIGS. 1 and 2 also illustrate a microelectronic component 102-2 coupled to the interposer 150 by a DB region 130-2 (via the DB interfaces 180-2A and 180-2B, as shown in FIG. 2). Although FIG. 1 depicts a particular number of microelectronic components 102 coupled to the interposer 150 by DB regions 130, this number and arrangement are simply illustrative, and a microelectronic assembly 100 may include any desired number and arrangement of microelectronic components 102 coupled to an interposer 150 by DB regions 130. Although a single reference numeral “108” is used to refer to the DB dielectrics of multiple different DB interfaces 180 (and different DB regions 130), this is simply for ease of illustration, and the DB dielectric 108 of different DB interfaces 180 (even within a single DB region 130) may have different materials and/or structures (e.g., in accordance with any of the embodiments discussed below with reference to FIG. 3). Similarly, although a single reference numeral “110” is used to refer to the DB contacts of multiple different DB interfaces 180 (and different DB regions 130), this is simply for ease of illustration, and the DB contacts 110 of different DB interfaces 180 (even within a single DB region 130) may have different materials and/or structures (e.g., in accordance with any of the embodiments discussed below with reference to FIG. 4).

The interposer 150 may include an insulating material 106 (e.g., one or more dielectric materials formed in multiple layers, as known in the art) and one or more conductive pathways 112 through the insulating material 106 (e.g., including conductive lines 114 and/or conductive vias 116, as shown). In some embodiments, the insulating material 106 of the interposer 150 may be an organic material, such as polyimide or polybenzoxazole, or may include an organic polymer matrix (e.g., epoxide) with a filler material (which may be inorganic, such as silicon nitride, silicon oxide, or aluminum oxide). In some such embodiments, the interposer 150 may be referred to as an “organic interposer.” In some embodiments, the insulating material 106 of an interposer 150 may be provided in multiple layers of organic buildup film. Organic interposers 150 may be less expensive to manufacture than semiconductor- or glass-based interposers, and may have electrical performance advantages due to the low dielectric constants of organic insulating materials 106 and the thicker lines that may be used (allowing for improved power delivery, signaling, and potential thermal benefits). Organic interposers 150 may also have larger footprints than can be achieved for semiconductor-based interposers, which are limited by the size of the reticle used for patterning.

Further, organic interposers 150 may be subject to less restrictive design rules than those that constrain semiconductor- or glass-based interposers, allowing for the use of design features such as non-Manhattan routing (e.g., not being restricted to using one layer for horizontal interconnects and another layer for vertical interconnects) and the avoidance of through-substrate vias (TSVs) such as through-silicon vias or through-glass vias (which may be limited in the achievable pitch, and may result in less desirable power delivery and signaling performance). Conventional integrated circuit packages including an organic interposer have been limited to solder-based attach technologies, which may have a lower limit on the achievable pitch that precludes the use of conventional solder-based interconnects to achieve the fine pitches desired for next generation devices. Utilizing an organic interposer 150 in a microelectronic assembly 100 with direct bonding, as disclosed herein, may leverage these advantages of organic interposers in combination with the ultra-fine pitch (e.g., the pitch 128 discussed below) achievable by direct bonding (and previously only achievable when using semiconductor-based interposers), and thus may support the design and fabrication of large and sophisticated die complexes that can achieve packaged system competition performance and capabilities not enabled by conventional approaches.

In other embodiments, the insulating material 106 of the interposer 150 may include a fire retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, or low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, and porous dielectrics). When the interposer 150 is formed using standard printed circuit board (PCB) processes, the insulating material 106 may include FR-4, and the conductive pathways 112 in the interposer 150 may be formed by patterned sheets of copper separated by buildup layers of the FR-4. In some such embodiments, the interposer 150 may be referred to as a “package substrate” or a “circuit board.”

In some embodiments, one or more of the conductive pathways 112 in the interposer 150 may extend between a conductive contact at the top surface of the interposer 150 (e.g., one of the DB contacts 110) and a conductive contact 118 at the bottom surface of the interposer 150. In some embodiments, one or more of the conductive pathways 112 in the interposer 150 may extend between different conductive contacts at the top surface of the interposer 150 (e.g., between different DB contacts 110 potentially in different DB regions 130, as discussed further below). In some embodiments, one or more of the conductive pathways 112 in the interposer 150 may extend between different conductive contacts 118 at the bottom surface of the interposer 150.

In some embodiments, an interposer 150 may only include conductive pathways 112, and may not contain active or passive circuitry. In other embodiments, an interposer 150 may include active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others). In some embodiments, an interposer 150 may include one or more device layers including transistors.

Although FIGS. 1 and 2 (and others of the accompanying drawings) illustrate a specific number and arrangement of conductive pathways 112 in the interposer 150, these are simply illustrative, and any suitable number and arrangement may be used. The conductive pathways 112 disclosed herein (e.g., including lines 114 and/or vias 116) may be formed of any appropriate conductive material, such as copper, silver, nickel, gold, aluminum, other metals or alloys, or combinations of materials, for example. Examples of some particular arrangements of liner materials 132 that may be part of conductive pathways 112 are discussed below with reference to FIGS. 9-10.

In some embodiments, a microelectronic component 102 may include an IC die (packaged or unpackaged) or a stack of an IC dies (e.g., a high-bandwidth memory dies stack). In some such embodiments, the insulating material of a microelectronic component 102 may include silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass-reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some further embodiments, the insulating material of a microelectronic component 102 may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material of a microelectronic component 102 may include silicon oxide or silicon nitride. The conductive pathways in a microelectronic component 102 may include conductive lines and/or conductive vias, and may connect any of the conductive contacts in the microelectronic component 102 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the microelectronic component 102). Example structures that may be included in the microelectronic components 102 disclosed herein are discussed below with reference to FIG. 36. In particular, a microelectronic component 102 may include active and/or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others). In some embodiments, a microelectronic component 102 may include one or more device layers including transistors. When a microelectronic component 102 includes active circuitry, power and/or ground signals may be routed through the interposer 150 and to/from a microelectronic component 102 through a DB region 130 (and further through intervening microelectronic components 102). In some embodiments, a microelectronic component 102 may take the form of any of the embodiments of the interposer 150 herein. Although the microelectronic components 102 of the microelectronic assembly 100 of FIG. 1 are single-sided components (in the sense that an individual microelectronic component 102 only has conductive contacts (e.g., DB contacts 110) on a single surface of the individual microelectronic component 102), in some embodiments, a microelectronic component 102 may be a double-sided (or “multi-level,” or “omni-directional”) component with conductive contacts on multiple surfaces of the component. Some particular examples of double-sided microelectronic components 102 are discussed below with reference to FIGS. 21-23.

Additional components (not shown), such as surface-mount resistors, capacitors, and/or inductors, may be disposed on the top surface or the bottom surface of the interposer 150, or embedded in the interposer 150. The microelectronic assembly 100 of FIG. 1 also includes a support component 182 coupled to the interposer 150. In the particular embodiment of FIG. 1, the support component 182 includes conductive contacts 118 that are electrically coupled to complementary conductive contacts 118 of the interposer 150 by intervening solder 120 (e.g., solder balls in a ball grid array (BGA) arrangement), but any suitable interconnect structures may be used (e.g., pins in a pin grid array arrangement, lands in a land grid array arrangement, pillars, pads and pillars, etc.). The solder 120 utilized in the microelectronic assemblies 100 disclosed herein may include any suitable materials, such as lead/tin, tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, tin/nickel/copper, tin/bismuth/copper, tin/indium/copper, tin/zinc/indium/bismuth, or other alloys. In some embodiments, the couplings between the interposer 150 and the support component 182 may be referred to as second-level interconnects (SLI) or multi-level interconnects (MLI).

In some embodiments, the support component 182 may be a package substrate (e.g., may be manufactured using PCB processes, as discussed above). In some embodiments, the support component 182 may be a circuit board (e.g., a motherboard), and may have other components attached to it (not shown). The support component 182 may include conductive pathways and other conductive contacts (not shown) for routing power, ground, and signals through the support component 182, as known in the art. In some embodiments, the support component 182 may include another IC package, an interposer, or any other suitable component. An underfill material 138 may be disposed around the solder 120 coupling the interposer 150 to the support component 182. In some embodiments, the underfill material 138 may include an epoxy material.

In some embodiments, the support component 182 may be a lower density component, while the interposer 150 and/or the microelectronic components 102 may be higher density components. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive lines and conductive vias) in a lower density component are larger and/or have a greater pitch than the conductive pathways in a higher density component. In some embodiments, a microelectronic component 102 may be a higher density component, and an interposer 150 may be a lower density component. In some embodiments, a higher density component may be manufactured using a dual damascene or single damascene process (e.g., when the higher density component is a die), while a lower density component may be manufactured using a semi-additive or modified semi-additive process (with small vertical interconnect features formed by advanced laser or lithography processes) (e.g., when the lower density component is a package substrate or an interposer). In some other embodiments, a higher density component may be manufactured using a semi-additive or modified semi-additive process (e.g., when the higher density component is a package substrate or an interposer), while a lower density component may be manufactured using a semi-additive or a subtractive process (using etch chemistry to remove areas of unwanted metal, and with coarse vertical interconnect features formed by a standard laser process) (e.g., when the lower density component is a PCB).

The microelectronic assembly 100 of FIG. 1 may also include a mold material 126. The mold material 126 may extend around one or more of the microelectronic components 102 on the interposer 150. In some embodiments, the mold material 126 may extend between multiple microelectronic components 102 on the interposer 150 and around the DB regions 130. In some embodiments, the mold material 126 may extend above one or more of the microelectronic components 102 on an interposer 150 (not shown). The mold material 126 may be an insulating material, such as an appropriate epoxy material. The mold material 126 may be selected to have a coefficient of thermal expansion (CTE) that may mitigate or minimize the stress between the microelectronic components 102 and the interposer 150 arising from uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the mold material 126 may have a value that is intermediate to the CTE of the interposer 150 (e.g., the CTE of the insulating material 106 of the interposer 150) and a CTE of the microelectronic components 102. In some embodiments, the mold material 126 used in a microelectronic assembly 100 may be selected at least in part for its thermal properties. For example, one or more mold materials 126 used in a microelectronic assembly 100 may have low thermal conductivity (e.g., conventional mold compounds) to retard heat transfer, or may have high thermal conductivity (e.g., mold materials including metal or ceramic particles with high thermal conductivity, such as copper, silver, diamond, silicon carbide, aluminum nitride, and boron nitride, among others) to facilitate heat transfer. Any of the mold materials 126 referred to herein may include one or more different materials with different material compositions.

The microelectronic assembly 100 of FIG. 1 may also include a TIM 154. The TIM 154 may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. The TIM 154 may be a thermal interface material paste or a thermally conductive epoxy (which may be a fluid when applied and may harden upon curing, as known in the art). The TIM 154 may provide a path for heat generated by the microelectronic components 102 to readily flow to the heat transfer structure 152, where it may be spread and/or dissipated. Some embodiments of the microelectronic assembly 100 of FIG. 1 may include a sputtered metallization (not shown) across the top surfaces of the mold material 126 and the microelectronic components 102; the TIM 154 (e.g., a solder TIM) may be disposed on this metallization.

The microelectronic assembly 100 of FIG. 1 may also include a heat transfer structure 152. The heat transfer structure 152 may be used to move heat away from one or more of the microelectronic components 102 (e.g., so that the heat may be more readily dissipated). The heat transfer structure 152 may include any suitable thermally conductive material (e.g., metal, appropriate ceramics, etc.), and may include any suitable features (e.g., a heat spreader, a heat sink including fins, a cold plate, etc.). In some embodiments, a heat transfer structure 152 may be or may include an integrated heat spreader (IHS).

The elements of a microelectronic assembly 100 may have any suitable dimensions. Only a subset of the accompanying drawings are labeled with reference numerals representing dimensions, but this is simply for clarity of illustration, and any of the microelectronic assemblies 100 disclosed herein may have components having the dimensions discussed herein. In some embodiments, the thickness 184 of the interposer 150 may be between 20 microns and 200 microns. In some embodiments, the thickness 188 of a DB region 130 may be between 0.1 microns and 5 microns. In some embodiments, a thickness 190 of a microelectronic component 102 may be between 10 microns and 780 microns. In some embodiments, a pitch 128 of the DB contacts 110 in a DB region 130 may be less than 20 microns (e.g., between 0.1 microns and 20 microns).

FIGS. 3-23 illustrate additional example microelectronic assemblies 100 and components thereof. Any of the features discussed with reference to any of FIGS. 3-23 herein may be combined with any other features to form a microelectronic assembly 100 or component thereof. For example, as discussed further below, FIG. 4 illustrates an embodiment of a DB interface 180 in which a DB contact 110 includes multiple different material portions, and FIG. 9 illustrates an embodiment of a DB interface 180 in which a liner material 132 is present between a DB contact 110 and the adjacent DB dielectric 108. These features of FIGS. 4 and 9 may be combined so that a DB interface 180, in accordance with the present disclosure, has DB contacts 110 with multiple different material portions and a liner material 132 between DB contacts 110 and adjacent DB dielectric 108. This particular combination is simply an example, and any combination may be used.

As noted above, a DB dielectric 108 may include one or more materials arranged in any desired manner. For example, FIG. 3 illustrates a DB interface 180 (which may be part of an interposer 150 or a microelectronic component 102) that includes DB dielectric 108 around DB contacts 110. In the particular embodiment of FIG. 3, the DB dielectric 108 may include a first portion 108A and a second portion 108B, with the second portion 108B between the first portion 108A and the bonding surface of the DB interface 180. The first portion 108A and the second portion 108B may have different material compositions. For example, in some embodiments, the first portion 108A may include silicon and oxygen (e.g., in the form of silicon oxide), and the second portion 108B may include silicon, oxygen, carbon, and nitrogen (e.g., in the form of silicon oxycarbonitride). The thickness 190A of the first portion 108A may be greater than the thickness 190B of the second portion 108B. For example, in some embodiments, the thickness 190B may be less than 5 nanometers (e.g., less than 3 nanometers), while the thickness 190A may be greater than 5 nanometers (e.g., between 50 nanometers and 5 microns). When the thickness 190A is greater than the thickness 190B, the first portion 108A may be referred to as a “bulk” material and the second portion 108B may be referred to as an “interface” material of the DB dielectric 108. Although FIG. 3 illustrates an embodiment in which the DB dielectric 108 includes two portions, a DB dielectric 108 may include more than two portions (e.g., arranged in layers parallel to the bonding surface of the DB interface 180).

As also noted above, a DB contact 110 may include one or more materials arranged in any desired manner. For example, FIG. 4 illustrates a DB interface 180 (which may be part of an interposer 150 or a microelectronic component 102) that includes DB dielectric 108 around DB contacts 110. In the particular embodiment of FIG. 4, the DB contacts 110 may include a first portion 110A and a second portion 110B, with the second portion 110B between the first portion 110A and the bonding surface of the DB interface 180. The first portion 110A and the second portion 110B may have different material compositions. For example, in some embodiments, the first portion 110A may include copper, and the second portion 110B may include a noble metal (e.g., silver or gold); in such embodiments, the second portion 110B may serve to improve the resistance of the DB contacts 110 to corrosion. The thickness 192A of the first portion 110A may be greater than the thickness 192B of the second portion 110B. For example, in some embodiments, the thickness 192B may be less than 5 nanometers, while the thickness 192A may be greater than 50 nanometers. When the thickness 192A is greater than the thickness 192B, the first portion 110A may be referred to as a “bulk” material and the second portion 110B may be referred to as an “interface” material of the DB contacts 110. Although FIG. 4 illustrates an embodiment in which the DB contacts 110 include two portions, a DB contact 110 may include more than two portions (e.g., arranged in layers parallel to the bonding surface of the DB interface 180). In some embodiments, a DB interface 180 may include a DB dielectric 108 with multiple portions and a DB contact 110 with multiple portions.

The footprints of the DB contacts 110 in a DB interface 180 may have any desired shape, and multiple DB contacts 110 may be arranged within a DB interface 180 in any desired manner (e.g., by the use of lithographic patterning techniques to form the DB contacts 110). For example, FIGS. 5-8 are top views of various arrangements of DB contacts 110 in a DB dielectric 108 of a DB interface 180. In the embodiment of FIG. 5, the DB contacts 110 have rectangular (e.g., square) footprints and are arranged in a rectangular array. In the embodiment of FIG. 6, the DB contacts 110 have cross-shaped footprints and are arranged in a triangular array. In the embodiment of FIG. 7, the DB contacts 110 are arranged in a rectangular array, and alternating rows of the DB contacts 110 have cross-shaped footprints and triangular footprints. In the embodiment of FIG. 8, the DB contacts 110 are arranged in a rectangular array, the DB contacts 110 have circular footprints, and the diameters of the footprints of the DB contacts 110 vary in a checkerboard pattern. DB contacts 110 included in a DB interface 180 may have any suitable combination of these and other footprint shapes, sizes, and arrangements (e.g., hexagonal arrays, oval footprints, etc.). In some particular embodiments, DB contacts 110 in a DB interface 180 may have footprints shaped as convex polygons (e.g., squares, rectangles, octagons, cross shapes, etc.) or circles.

As noted above, in some embodiments, a liner material may be present between a DB contact 110 and the adjacent DB dielectric 108. For example, FIG. 9 illustrates a portion of an interposer 150 and its DB interface 180. In the embodiment of FIG. 9, a liner material 132 is present between the DB contacts 110 and the adjacent DB dielectric 108. The liner material 132 may serve as a diffusion barrier (e.g., to limit diffusion between the DB contacts 110 and the adjacent DB dielectric 108, such as the copper diffusion that may occur when the DB contacts 110 include copper and the DB dielectric 108 includes silicon oxide) and/or as an adhesion promoter (e.g., to improve the strength of the mechanical interface between the DB contacts 110 and the adjacent DB dielectric 108). In the particular embodiment of FIG. 9, the liner material 132 may not be present around the vias 116 and/or the lines 114 through the insulating material 106 of the interposer 150. In other embodiments, the liner material 132 may also be present around the vias 116 and/or the lines 114; such an embodiment is illustrated in FIG. 10. In some embodiments, a liner material 132 may only be present around the vias 116 and/or the lines 114, but not around the DB contacts 110 (not shown). In the embodiment of FIG. 9, the liner material 132 may be a conductive material (e.g., may include cobalt, ruthenium, or tantalum and nitrogen (e.g., in the form of tantalum nitride)), or a non-conductive material (e.g., silicon and nitrogen (e.g., in the form of silicon nitride), or diamond-like carbon). In the embodiment of FIG. 10, the liner material 132 may be a non-conductive material. In still other embodiments, no liner material 132 may be present in an interposer 150. Although various embodiments of the use of liner material 132 are depicted in FIGS. 9 and 10 and discussed with respect to their presence in an interposer 150, this is simply for ease of illustration, and DB interfaces 180 of microelectronic components 102 may also include liner materials 132 (e.g., only around the DB contacts 110, and/or around lines and vias in a metallization stack of the microelectronic component 102).

In some embodiments, lithographic via techniques may be used to form one or more layers of metallization in an interposer 150 (e.g., in an organic interposer 150) or a microelectronic component 102. For example, FIG. 11 illustrates a portion of an interposer 150 and its DB interface 180. In the embodiment of FIG. 11, three different layers of insulating material 106 are shown (labeled as 106A, 106B, and 106C). Within the “top” layer 106A (the layer closest to the DB interface 180), vias 116 may be patterned using lithographic techniques (e.g., “zero-misalignment” techniques) so that their side faces are aligned with side faces of the lines 114 on which they land. In “lower” layers (e.g., the layer 106B), vias 116 may be patterned using conventional techniques and the side faces of the vias 116 may not align with side faces of the lines 114 on which they land. More generally, a via 116 formed lithographically may have any desired footprint (e.g., a non-circular footprint). In the embodiment of FIG. 11, the DB contacts 110 may be “pads” in conductive contact with the vias 116 of the layer 106A. The use of lithographic via techniques in the formation of the DB interface 180 may result in an extremely flat DB interface 180 due to the planarization (e.g., chemical mechanical polishing) operations performed during lithographic via fabrication, and flat DB interfaces 180 may more reliably form direct bonds than more “uneven” DB interfaces 180. Thus, the use of lithographic via techniques to form the DB contacts 110 of a DB interface 180 may support a mechanically and electrically reliable DB region 130.

In some embodiments, lithographic via techniques to be used to form the DB contacts 110 in a DB interface 180 of an interposer 150 (e.g., in an organic interposer 150) or a microelectronic component 102. For example, FIG. 12 illustrates a portion of an interposer 150 and its DB interface 180. In the embodiment of FIG. 12, a DB contact 110 includes a via 116 and a line 114 on which the via 116 lands; these vias 116 may be patterned using lithographic techniques (e.g., so that the side faces of the vias 116 are aligned with side faces of the lines 114 on which they land). The DB dielectric 108 may contact the vias 116 and lines 114 of the DB contacts 110, as shown. Metallization in the insulating material 106 may be patterned using lithographic techniques or conventional techniques. Although various embodiments of vias 116/lines 114 are depicted in FIGS. 11 and 12 and discussed with respect to their presence in an interposer 150, this is simply for ease of illustration, and DB interfaces 180 of microelectronic components 102 may also include lithographically patterned vias 116/lines 114 in the DB interfaces 180 and/or the other metallization.

In the embodiment of FIGS. 1 and 2, the DB contacts 110 are shown as pads in contact with vias 116 in the underlying insulating material 106. In other embodiments, the DB contacts 110 may be vias themselves. For example, FIG. 13 illustrates an embodiment in which the DB contacts 110 are vias in contact with pads in the insulating material 106; as shown, the DB contacts 110 may be narrower than the pads with which they are in contact.

The microelectronic assembly 100 of FIGS. 1 and 2, and others of the microelectronic assemblies 100 disclosed herein, may be manufactured in any suitable manner. For example, FIGS. 14-17 are side, cross-sectional views of example stages in the manufacture of a portion of the microelectronic assembly 100 of FIGS. 1 and 2, in accordance with various embodiments. Although the operations discussed with reference to FIGS. 14-17 may be illustrated with reference to particular embodiments of the microelectronic assemblies 100 disclosed herein, the manufacturing methods discussed with reference to FIGS. 14-17 may be used to form any suitable microelectronic assemblies 100 operations are illustrated once each and in a particular order in FIGS. 14-17, but the operations may be reordered and/or repeated as desired (e.g., with different operations performed in parallel when manufacturing multiple microelectronic assemblies 100 simultaneously). The manufacturing processes discussed below with reference to FIGS. 14-17 may be particularly advantageous when the interposer 150 is an organic interposer, and may also be advantageous for glass-based or semiconductor-based interposers (e.g., glass-based or silicon-based interposers in which the underlying glass or silicon wafer has already been thinned, and TSVs formed, before any direct bonding operations). However, any suitable manufacturing processes may be used to manufacture any of the microelectronic assemblies 100 disclosed herein.

FIG. 14 illustrates an assembly including an interposer 150 mounted on a carrier 104. The interposer 150 includes two exposed DB interfaces 180-1 and 180-2. The carrier 104 may include any suitable material, and in some embodiments, may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). When the interposer 150 is an organic interposer, the interposer 150 may be advantageously manufactured on the carrier 104, which may provide a mechanically stable surface on which the layers of the interposer 150 may be formed.

FIG. 15 illustrates an assembly subsequent to direct bonding microelectronic components 102-1 and 102-2 to the interposer 150/carrier 104 of FIG. 14. In particular, DB interfaces 180 (not labeled) of the microelectronic components 102 may be brought into contact with the DB interfaces 180 of the interposer 150, and heat and/or pressure to be applied to bond the contacting DB interfaces 180 to form DB regions 130 (with DB regions 130-1 and 130-2 corresponding to the DB interfaces 180-1 and 180-2, respectively).

FIG. 16 illustrates an assembly subsequent to providing a mold material 126 around the microelectronic components 102 and on the surface of the interposer 150 of the assembly of FIG. 15. In some embodiments, the mold material 126 may extend above and remain above the microelectronic components 102, while in other embodiments, the mold material 126 may be polished back to expose the top surfaces of the microelectronic components 102, as shown.

FIG. 17 illustrates an assembly subsequent to removing the carrier 104 from the assembly of FIG. 16, and providing solder 120 on the newly exposed conductive contacts 118. The assembly of FIG. 17 may itself be a microelectronic assembly 100, as shown. Further manufacturing operations may be performed on the microelectronic assembly 100 of FIG. 17 to form other microelectronic assemblies 100; for example, the solder 120 may be used to couple the microelectronic assembly 100 of FIG. 17 to a support component 182, and a TIM 154 and heat transfer structure 152 may be provided on the top surface of the microelectronic assembly 100 of FIG. 17, forming the microelectronic assembly 100 of FIGS. 1 and 2.

Different DB regions 130 in a microelectronic assembly 100 may include different DB dielectrics 108. For example, FIG. 18 illustrates a microelectronic assembly 100 in which a DB region 130-1 includes a DB dielectric 108-1 and a DB region 130-2 includes a different DB dielectric 108-2. The DB dielectrics 108-1 and 108-2 may differ in their material composition and/or their structure. In some embodiments, DB dielectrics 108 in different DB regions 130 may be selected to have different thermal conductivities so as to facilitate and/or limit heat transfer between the interposer 150 and the microelectronic components 102. For example, the DB dielectric 108-1 may have a higher thermal conductivity than the DB dielectric 108-2, resulting in greater heat transfer between the microelectronic component 102-1 and the interposer 150 than between the microelectronic component 102-2 and the interposer 150. In some such embodiments, the DB dielectric 108-1 may include silicon and nitrogen (e.g., in the form of silicon nitride) and the DB dielectric 108-2 may include silicon and oxygen (e.g., in the form of silicon oxide); silicon nitride may have a higher thermal conductivity than silicon oxide, and thus the use of silicon nitride as the DB dielectric 108-1 may enhance local heat transfer from the microelectronic component 102-1 to the interposer 150, while the use of silicon oxide as the DB dielectric 108-2 may mitigate thermal cross-talk through the interposer 150 between the microelectronic component 102-1 and the microelectronic component 102-2.

In some embodiments, the density of the DB contacts 110 (i.e., the proportion of the area of a bonding surface of a DB interface 180 occupied by DB contacts 110) may differ between different DB regions 130. In some embodiments, this differing density may be due to one DB region 130 requiring fewer electrical pathways than another DB region 130. In other embodiments, this differing density may be used to enhance or suppress heat transfer, with greater density of DB contacts 110 (and therefore a higher proportion of thermally conductive metal) being used to enhance heat transfer and lesser density of DB contacts 110 (and therefore a lower portion of thermally conductive metal) being used to suppress heat transfer. For example, FIG. 19 illustrates an embodiment in which the density of DB contacts 110 is greater in the DB region 130-1 than in the DB region 130-2 to enhance heat transfer between the microelectronic component 102-1 and the interposer 150 and to reduce heat transfer between the microelectronic component 102-2 and the interposer 150. FIG. 19 illustrates different densities of DB contacts 110 being accompanied by the use of different DB dielectrics 108 in different DB regions 130, but in some embodiments, two DB regions 130 may have different densities of DB contacts 110 while having DB dielectrics 108 with the same material composition.

In the embodiment of FIGS. 1 and 2, the DB dielectric 108 extends outside of the DB regions 130, covering the remainder of the top surface of the interposer 150. In other embodiments, a different material may be disposed at the top surface of the interposer 150 outside of the DB regions 130. For example, FIG. 20 illustrates a microelectronic assembly 100 in which a material 134, different from the DB dielectrics 108-1 and 108-2, is disposed at the top surface of the interposer 150 (e.g., in contact with the mold material 126). In some embodiments, the material 134 may include one or more dielectric materials, such as one or more organic or inorganic dielectric materials. For example, the material 134 may include an inorganic dielectric material that includes silicon and nitrogen (e.g., in the form of silicon nitride); silicon and oxygen (e.g., in the form of silicon oxide); or silicon, carbon, and nitrogen (e.g., in the form of silicon carbonitride); or the material 134 may include an organic dielectric material, such as a particle-filled epoxide, a polyimide, a particle-filled polyimide, or polybenzoxazole. In some embodiments, the material 134 may be a dielectric material, and an additional conductive material (e.g., a metal such as aluminum or copper) may be disposed on the material 134.

A microelectronic assembly 100 may include multiple “tiers” of microelectronic components 102 coupled by direct bonding. For example, FIGS. 21A and 21B illustrate microelectronic assemblies 100 in which a microelectronic component 102-1 includes two DB interfaces 180 (not labeled) at its top surface, and microelectronic components 102-3 and 102-4 with their own DB interfaces 180 (not labeled) at the bottom surfaces are coupled to the microelectronic component 102-1 via DB regions 130-3 and 130-4, respectively. Similarly, the microelectronic component 102-2 includes a DB interface 180 (not labeled) at its top surface, and a microelectronic component 102-5 with its own DB interface 180 (not labeled) at its bottom surface is coupled to the microelectronic component 102-2 via a DB region 130-5. The microelectronic assemblies 100 of FIG. 21 may thus be described as having two tiers of direct bonded microelectronic components 102. The microelectronic assemblies 100 of FIGS. 21A and 21B share many features, and FIG. 21B illustrates a particular embodiment in which the microelectronic component 102-1 includes an embedded microelectronic component 102-6 (e.g., an embedded die), and the DB region 130-4 is at the top face of the embedded microelectronic component 102-6. In some embodiments, the embedded microelectronic component 102-6 may be a higher density component and the microelectronic component 102-1 may be a lower density component. The microelectronic component 102-1 may include one or more conductive structures 195 that conductively couple contacts (not shown) at the bottom surface of the embedded microelectronic component 102-6 to the DB contacts 110 at the bottom surface of the microelectronic component 102-1. More generally, any microelectronic component 102 disclosed herein may include one or more dies and may have different types of pass-through conductive interconnects, such as copper pillars and TSVs (e.g., through-silicon vias).

In some embodiments, the microelectronic components 102-1 and 102-2 in the first tier of the microelectronic assembly 100 of FIG. 21 may include conductive structures 194 that extend between the DB regions 130 at their top and bottom surfaces, providing conductive pathways for power, ground, and/or signals to the microelectronic components 102 in the second tier (i.e., the microelectronic components 102-3, 102-4, and 102-5). In some embodiments, such a conductive structure 194 may include one or more TSVs, including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide), such as through-silicon vias when the microelectronic components 102-1 and 102-2 include silicon substrates or through-glass vias when the microelectronic components 102-1 and 102-2 include glass substrates. In some embodiments, the microelectronic components 102-1 and 102-2 in a first tier may be passive (e.g., including no transistors) or active (e.g., including transistors in the form of memory circuitry and/or power delivery circuitry).

In the embodiment of FIG. 21, a mold material 126 may extend up to and may laterally surround the microelectronic components 102 in the second tier, and in some embodiments (not shown), the mold material 126 may cover the top surfaces of the microelectronic components 102 in the second tier. As shown in FIG. 21, in some embodiments, the top surface of the mold material 126 may be coplanar with the exposed DB interfaces 180. In some embodiments, a microelectronic assembly 100 including exposed DB interfaces 180 may have a temporary, removable protective material (e.g., an adhesive material, not shown) on the exposed DB interfaces 180 to protect them until direct bonding operations are performed. Microelectronic assemblies 100 including multiple tiers of microelectronic components 102 may be formed in a manner discussed above with reference to FIGS. 14-17, with the additional tiers of microelectronic components 102 coupled to the preceding assemblies prior to deposition of the mold material 126. In some other embodiments, a microelectronic assembly 100 including multiple tiers of microelectronic components 102 may be formed by first assembling the tiers of microelectronic components 102, and then coupling the assembled tiers to an interposer 150 as discussed above with reference to FIG. 15. A microelectronic assembly 100 may not be limited to two tiers of microelectronic components 102, but may include three or more tiers, as desired. Further, although the microelectronic components 102 in an individual tier in FIG. 21 are depicted as having a same height, this is simply for ease of illustration, and microelectronic components 102 in any individual tier in a microelectronic assembly 100 may have different heights. Further, not every microelectronic component 102 in a microelectronic assembly 100 may be part of a stack of multiple microelectronic components 102; for example, in some variants of the microelectronic assembly 100 of FIG. 21, no microelectronic component 102-5 may be present on top of the microelectronic component 102-2 (and thus the microelectronic component 102-2 may not include conductive structures 194 (e.g., may not include TSVs)).

In some embodiments, a microelectronic assembly 100 may include one or more DB interfaces 180 exposed at a surface of the microelectronic assembly 100. For example, FIG. 22 illustrates a microelectronic assembly 100 similar to that of FIG. 21, but in which the second tier of microelectronic components 102 is not present and the corresponding DB interfaces 180 (i.e., the DB interfaces 180-3, 180-4, and 180-5) are exposed at the top surfaces of the microelectronic components 102-1 and 102-2. Such a microelectronic assembly 100 may be useful when a customer or other entity wishes to couple, via direct bonding, their own additional microelectronic components 102 (e.g., the microelectronic components 102-3, 102-4, and 102-5 of FIG. 21) to the top surfaces of the microelectronic assembly 100 of FIG. 22 via the exposed DB interfaces 180. FIG. 22 illustrates a particular embodiment in which DB interfaces 180 are exposed at top surfaces of a first tier of microelectronic components 102, but a microelectronic assembly 100 may include more than one tier of microelectronic components 102 with DB interfaces 180 exposed at top surfaces of microelectronic components 102 in a second (or higher) tier. For example, FIG. 23 illustrates a microelectronic assembly 100 similar to that of FIG. 21, but in which the microelectronic components 102-3, 102-4, and 102-5 have DB interfaces 180 that are exposed at the top surface of the microelectronic assembly 100. As shown in FIG. 23, in some embodiments, the top surface of the mold material 126 may be coplanar with the exposed DB interfaces 180. Although various ones of the preceding drawings illustrate DB regions 130 at a single surface of the interposer 150 (e.g., the top surface), a microelectronic assembly 100 may include DB regions 130 at multiple surfaces of an interposer 150.

A microelectronic component 102 (e.g., a die) may be manufactured by singulating multiple microelectronic components 102 (either completely or partially manufactured) from each other (e.g., when multiple microelectronic components 102 are manufactured starting from a single wafer 1500, as discussed below with reference to FIG. 35). Conventional singulation processes may result in debris that can contaminate the surfaces of a microelectronic component 102, and the level of debris generated by conventional singulation processes may contaminate and/or increase the roughness of a DB interface 180 so as to prevent reliable direct bonding. In some embodiments, the manufacture of a microelectronic component 102 having a DB interface 180 may include a singulation process that results in less debris at the DB interface 180 than conventional singulation processes, and thus increases the quality of the bond in a DB region 130 of a microelectronic assembly 100. Some such low-debris singulation processes may include the formation of a trench at a periphery of the microelectronic component 102 prior to singulation; as discussed further below, such a trench may “capture” the singulation debris, leaving the DB interface 180 relatively debris-free.

For example, FIGS. 24A-24B are various views of a microelectronic assembly 100 including a microelectronic component 102 having a DB interface 180 and a peripheral trench 308, in accordance with various embodiments. FIG. 24A is a side, cross-sectional view of the microelectronic assembly 100, and FIG. 24B is a bottom view of the microelectronic component 102 of the microelectronic assembly 100 of FIG. 24A, showing the DB interface 180 and the peripheral trench 308 at the bottom surface of the microelectronic component 102. In the microelectronic assembly 100 of FIG. 24, the DB interface 180 of the microelectronic component 102 may be bonded to a DB interface 180 of an interposer 150, forming a DB region 130; the details of the DB interfaces 180 and DB region 130 of the microelectronic assembly 100 of FIG. 24 are omitted for clarity of illustration, and may take any of the forms disclosed herein. Although FIG. 24 illustrates a microelectronic assembly 100 including a microelectronic component 102 (including a peripheral trench 308) bonded to a interposer 150, this is simply an example, and a microelectronic assembly 100 may include one microelectronic component 102 (including a peripheral trench 308) bonded to any other suitable microelectronic component 102 (which may or may not include a peripheral trench 308).

In some embodiments, a microelectronic component 102 may include a raised burr 310 in the peripheral trench 308. As used herein, a “burr” may take the form of a protrusion from a surface (e.g., in a direction normal to the surface or parallel to the surface). Like the peripheral trench 308, the burr 310 may extend around a perimeter of the microelectronic component 102 and may be located at the far edge of the peripheral trench 308, as illustrated in FIG. 24B. The burr 310 may be a singulation artifact (e.g., arising from laser scribe, plasma dicing, and blade saw singulation), and may include a mix of various ablated materials of the microelectronic component 102; examples of particular burrs 310 are discussed below with reference to FIGS. 25-27.

The dimensions of a peripheral trench 308, and a burr 310 therein, may take any suitable form. In some embodiments, the depth 312 of a peripheral trench 308 may be between 2 microns and 25 microns (e.g., between 4 microns and 12 microns); examples of microelectronic components 102 having peripheral trenches 308 with different depths 312 are discussed below with reference to FIGS. 25-27. In some embodiments, the width 314 of a peripheral trench 308 may be greater than 2 microns (e.g., between 3 microns and 7 microns). The height 316 of a burr 310 may be less that a depth 312 of the peripheral trench 308 in which the burr 310 is disposed, and thus the burr 310 may not interfere with direct bonding at the DB interface 180. In some embodiments, the height 316 of a burr 310 may be less than 500 nanometers. In some embodiments, a DB interface 180 may have a root-mean-square surface roughness that is less than 0.5 nanometers (e.g., less than 0.3 nanometers).

In some embodiments, a peripheral trench 308 may extend through a DB interface 180 but not into the underlying metallization of the microelectronic component 102. For example, FIG. 25 is a side, cross-sectional view of an example microelectronic component 102 having a DB interface 180 (including DB contacts 110 and a DB dielectric 108, as shown), a metallization stack 304, and a substrate 302. The metallization stack 304 may be between the DB interface 180 and the substrate 302. The metallization stack 304 may take the form of any of the metallization stacks disclosed herein (e.g., the metallization stacks 1619 discussed below with reference to FIG. 36), and the substrate 302 may take the form of any of the substrates disclosed herein (e.g., the substrate 1602 discussed below with reference to FIG. 36). The microelectronic component 102 of FIG. 25 may include a peripheral trench 308 that extends through the DB interface 180 but does not extend into the metallization stack 304; in some such embodiments, the depth 312 of the peripheral trench 308 may be equal to the thickness of the DB dielectric 108. The burr 310 may be disposed in the peripheral trench 308 on the metallization stack 304, and may include material of the metallization stack 304 and material of the substrate 302 (e.g., metal, semiconductor, and dielectric materials ablated during singulation of the metallization stack 304 and the substrate 302, as discussed below with reference to FIGS. 29-31).

A peripheral trench 308 may extend through a DB interface 180 and into the underlying metallization of a microelectronic component 102. For example, a peripheral trench 308 may extend through a DB interface 180 and into, but not through, the underlying metallization of the microelectronic component 102. For example, FIG. 26 is a side, cross-sectional view of an example microelectronic component 102 similar to that of FIG. 25, but including a peripheral trench 308 that extends through the DB interface 180 and into the metallization stack 304 without going through the metallization stack 304; in some such embodiments, the depth 312 of the peripheral trench 308 may be equal to the sum of the thickness of the DB dielectric 108 and the thickness of the portion of the metallization stack 304 through which the peripheral trench 308 extends. The burr 310 may be disposed in the peripheral trench 308 on the metallization stack 304, and may include material of the metallization stack 304 and material of the substrate 302 (e.g., due to singulation of the metallization stack 304 and the substrate 302, as discussed below with reference to FIGS. 29-31).

In some embodiments, a peripheral trench 308 may extend through a DB interface 180 and through the underlying metallization of a microelectronic component 102. For example, FIG. 27 is a side, cross-sectional view of an example microelectronic component 102 similar to that of FIGS. 25 and 26, but including a peripheral trench 308 that extends through the DB interface 180 and through the metallization stack 304. In some such embodiments, the depth 312 of the peripheral trench 308 may be equal to the sum of the thickness of the DB dielectric 108 and the height of the metallization stack 304. The burr 310 may be disposed in the peripheral trench 308 on the substrate 302, and may include material of the substrate 302 (e.g., due to singulation of the substrate 302, as discussed below with reference to FIGS. 29-31).

In some embodiments, a peripheral trench 308 may extend through a DB interface 180, through the underlying metallization of a microelectronic component 102, and into a substrate of the microelectronic component 102. For example, FIG. 28 is a side, cross-sectional view of an example microelectronic component 102 similar to that of FIGS. 25-27, but including a peripheral trench 308 that extends through the DB interface 180, through the metallization stack 304, and into the substrate 302. In some such embodiments, the depth 312 of the peripheral trench 308 may be equal to the sum of the thickness of the DB dielectric 108, the height of the metallization stack 304, and the thickness of the portion of the substrate 302 through which the peripheral trench 308 extends. The burr 310 may be disposed in the peripheral trench 308 on the substrate 302, and may include material of the substrate 302 (e.g., as discussed below with reference to FIGS. 29-31).

A microelectronic component 102 having a peripheral trench 308 may be formed using any suitable technique. For example, FIGS. 29-31 are side, cross-sectional views of example stages in the manufacture of a microelectronic component having a DB interface and a peripheral trench, in accordance with various embodiments. Although the operations discussed with reference to FIGS. 29-31 may be illustrated with reference to particular embodiments of the microelectronic components 102 disclosed herein, the manufacturing methods discussed with reference to FIGS. 29-31 may be used to form any suitable microelectronic component 102. In particular, the operations of FIGS. 29-31 are discussed with reference to the manufacture of the particular microelectronic component 102 illustrated in FIG. 25, but the operations of FIGS. 29-31 may be modified accordingly to manufacture any other suitable ones of the microelectronic components 102 disclosed herein. Operations are illustrated once each and in a particular order in FIGS. 29-31, but the operations may be reordered and/or repeated as desired (e.g., with different operations performed in parallel when manufacturing multiple microelectronic components 102 simultaneously).

FIG. 29 illustrates an assembly including an unsingulated substrate 322, an unsingulated metallization stack 324, and multiple DB interfaces 180 on the unsingulated metallization stack 324. The assembly of FIG. 29 may represent a stage in the manufacturing of a microelectronic component 102 in which multiple partially completed microelectronic components 102 are still part of a single assembly.

FIG. 30 illustrates an assembly subsequent to forming unsingulated trenches 326 in the dicing lanes of the assembly of FIG. 29. The unsingulated trenches 326 may be formed to a depth 312 equal to the desired depth 312 of the peripheral trenches 308; in the particular embodiment of FIG. 30, the unsingulated trenches 326 extend through the DB dielectric 108 but not into the unsingulated metallization stack 324 (e.g., as discussed above with reference to the microelectronic component 102 of FIG. 25), but in other embodiments, the unsingulated trenches 326 may extend into the unsingulated metallization stack 324, through the unsingulated metallization stack 324, and/or into the unsingulated substrate 322 (e.g., as discussed above with reference to the microelectronic components 102 of FIGS. 26, 27, and 28, respectively). The unsingulated trenches 326 may be formed using a lithographic patterning and etch technique. For example, a resist material may be deposited on the assembly of FIG. 29, this resist material may be lithographically patterned to form openings corresponding to the locations of the unsingulated trenches 326, one or more etch techniques may be used to remove the material of the assembly of FIG. 29 to form the unsingulated trenches 326, and then the resist material may be removed. The width of the unsingulated trenches 326 may be selected based on the desired width 314 of the peripheral trenches 308 and the amount of material that will be removed by subsequent cutting operations discussed below with reference to FIG. 31 (e.g., the width of a blade of a dicing saw, or the lane width of the mask used for a reactive ion etching (RIE) process, or the width of a laser ablation pattern).

FIG. 31 illustrates an assembly subsequent to making cuts in unsingulated trenches 326 of the assembly of FIG. 30 so as to separate multiple ones of the microelectronic components 102. The cutting operations may leave the peripheral trenches 308 at the perimeter of each microelectronic component 102, and may generate debris that accumulates as burrs 310 at the edges of the peripheral trenches 308, as shown; other debris generated during cutting may be largely contained within the peripheral trenches 308, and thus may not substantially contaminate the DB interface 180 of the microelectronic components 102. Any suitable cutting techniques may be used to singulate the microelectronic components 102, such as laser scribing, blade sawing, stealth dicing, or RIE.

As noted above, different techniques may be used to perform the cutting operations that separate multiple ones of the microelectronic components 102. Different ones of these techniques may enable control of the shape of the profiles of side surfaces of the microelectronic components 102. For example, some cutting techniques like RIE may enable selective curving, rounding, and/or angling of the side surfaces and/or corners of the microelectronic components 102; such curved, rounded, and/or angled surfaces/corners may impart mechanical benefits to the microelectronic components 102 (e.g., reducing stress-related failure modes) by reducing or eliminating mechanical stresses that can arise due to sharp material geometries. For example, FIG. 32A illustrates a microelectronic component 102 having convex side surfaces, while FIG. 32B illustrates a microelectronic component 102 having concave side surfaces. FIG. 32C illustrates a microelectronic component 102 having angled side surfaces; in the embodiment of FIG. 32C, the angled side surfaces result in a substrate 302 that widens toward the DB interface 180, but in other embodiments, the orientation of the angled side surfaces may be reversed so that the substrate 302 narrows toward the DB interface 180. In some embodiments, the side surfaces and/or corners of a microelectronic component 102 may be stepped (e.g., having a “step cut” arising from the initial use of a wider dicing blade followed by the use of a narrower dicing blade). For example, FIG. 33A illustrates a microelectronic component 102 having stepped side surfaces; in the embodiment of FIG. 33A, the stepped side surfaces result in a substrate 302 that widens toward the DB interface 180, but in other embodiments, the orientation of the stepped side surfaces may be reversed so that the substrate 302 narrows toward the DB interface 180. In some embodiments, the side surfaces and/or corners of a microelectronic component 102 may be jagged (e.g., due to laser scribing), in addition to or instead of being curved or angled, etc. For example, FIG. 33B illustrates a microelectronic component 102 having jagged side surfaces; in the embodiment of FIG. 33B, the jagged side surfaces result in a substrate 302 that widens toward the DB interface 180, but in other embodiments, the orientation of the stepped side surfaces may be reversed so that the substrate 302 narrows toward the DB interface 180. FIG. 34 is a bottom view of an example microelectronic component 102 having rounded corners. Rounded (e.g., chamfered) corners may be created using an appropriate mask during a plasma etch process, and may advantageously reduce mechanical stress in the microelectronic component 102; any of the microelectronic components 102 disclosed herein may include such rounded corners.

The microelectronic components 102 and microelectronic assemblies 100 disclosed herein may be included in any suitable electronic component. FIGS. 35-38 illustrate various examples of apparatuses that may include, or be included in, as suitable, any of the microelectronic components 102 and microelectronic assemblies 100 disclosed herein.

FIG. 35 is a top view of a wafer 1500 and dies 1502 that may be included in any of the microelectronic components 102 disclosed herein. For example, a die 1502 may serve as a microelectronic component 102, or may be included in a microelectronic component 102. The wafer 1500 may be composed of semiconductor material and may include one or more dies 1502 having IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which the dies 1502 are separated from one another to provide discrete “chips” of the semiconductor product; the singulation process may include the method illustrated in FIGS. 29-31, and thus the dies 1502 may include a peripheral trench 308 and a burr 310, as discussed above. The die 1502 may include one or more transistors (e.g., some of the transistors 1640 of FIG. 36, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 1500 or the die 1502 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a same die 1502 as a processing device (e.g., the processing device 1802 of FIG. 38) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 36 is a side, cross-sectional view of an IC device 1600 that may be included in any of the microelectronic components 102 disclosed herein. For example, an IC device 1600 (e.g., as part of a die 1502, as discussed above with reference to FIG. 35) may serve as a microelectronic component 102, or may be included in a microelectronic component 102. One or more of the IC devices 1600 may be included in one or more dies 1502 (FIG. 35). The IC device 1600 may be formed on a substrate 1602 (e.g., the wafer 1500 of FIG. 35) and may be included in a die (e.g., the die 1502 of FIG. 35). The substrate 1602 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate 1602. Although a few examples of materials from which the substrate 1602 may be formed are described here, any material that may serve as a foundation for an IC device 1600 may be used. The substrate 1602 may be part of a singulated die (e.g., the dies 1502 of FIG. 35) or a wafer (e.g., the wafer 1500 of FIG. 35).

The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 36 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), or high-electron-mobility transistors (HEMT). Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

The S/D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1602 may follow the ion-implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in FIG. 36 as interconnect layers 1606-1610). For example, electrically conductive features of the device layer 1604 (e.g., the gate 1622 and the S/D contacts 1624) may be electrically coupled with the interconnect structures 1628 of the interconnect layers 1606-1610. The one or more interconnect layers 1606-1610 may form a metallization stack (also referred to as an “ILD stack”) 1619 of the IC device 1600.

The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in FIG. 36). Although a particular number of interconnect layers 1606-1610 is depicted in FIG. 36, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures 1628 may include lines 1628 a and/or vias 1628 b filled with an electrically conductive material such as a metal. The lines 1628 a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628 a may route electrical signals in a direction in and out of the page from the perspective of FIG. 36. The vias 1628 b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1602 upon which the device layer 1604 is formed. In some embodiments, the vias 1628 b may electrically couple lines 1628 a of different interconnect layers 1606-1610 together.

The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in FIG. 36. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

A first interconnect layer 1606 may be formed above the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628 a and/or vias 1628 b, as shown. The lines 1628 a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.

A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628 b to couple the lines 1628 a of the second interconnect layer 1608 with the lines 1628 a of the first interconnect layer 1606. Although the lines 1628 a and the vias 1628 b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628 a and the vias 1628 b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual damascene process) in some embodiments.

A third interconnect layer 1610 (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.

The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In FIG. 36, the conductive contacts 1636 are illustrated as taking the form of bond pads. The conductive contacts 1636 may be electrically coupled with the interconnect structures 1628 and configured to route the electrical signals of the transistor(s) 1640 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1636 to mechanically and/or electrically couple a chip including the IC device 1600 with another component (e.g., a circuit board). The IC device 1600 may include additional or alternate structures to route the electrical signals from the interconnect layers 1606-1610; for example, the conductive contacts 1636 may include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG. 37 is a side, cross-sectional view of an IC device assembly 1700 that may include any of the microelectronic components 102 and/or microelectronic assemblies 100 disclosed herein. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first face 1740 of the circuit board 1702 and an opposing second face 1742 of the circuit board 1702; generally, components may be disposed on one or both faces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may include any of the embodiments of the microelectronic assemblies 100 disclosed herein (e.g., may include multiple microelectronic components 102 coupled together by direct bonding).

In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

The IC device assembly 1700 illustrated in FIG. 37 includes a package-on-interposer structure 1736 coupled to the first face 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702, and may include solder balls (as shown in FIG. 37), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in FIG. 37, multiple IC packages may be coupled to the package interposer 1704; indeed, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (the die 1502 of FIG. 35), an IC device (e.g., the IC device 1600 of FIG. 36), or any other suitable component. Generally, the package interposer 1704 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the package interposer 1704 may couple the IC package 1720 (e.g., a die) to a set of BGA conductive contacts of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in FIG. 37, the IC package 1720 and the circuit board 1702 are attached to opposing sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to a same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by way of the package interposer 1704.

In some embodiments, the package interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to TSVs 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.

The IC device assembly 1700 illustrated in FIG. 37 includes a package-on-package structure 1734 coupled to the second face 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling components 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 38 is a block diagram of an example electrical device 1800 that may include any of the microelectronic components 102 and/or microelectronic assemblies 100 disclosed herein. For example, any suitable ones of the components of the electrical device 1800 may include one or more of the IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein. A number of components are illustrated in FIG. 38 as included in the electrical device 1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in FIG. 38, but the electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1824 or audio output device 1808 may be coupled.

The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.

The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.

The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 is a microelectronic component, including: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

Example 2 includes the subject matter of Example 1, and further specifies that the trench has a depth greater than 1 micron.

Example 3 includes the subject matter of any of Examples 1-2, and further specifies that the trench has a depth between 2 microns and 25 microns.

Example 4 includes the subject matter of any of Examples 1-3, and further specifies that the trench has a width that is greater than 2 microns.

Example 5 includes the subject matter of any of Examples 1-4, and further specifies that the trench extends into a metallization stack of the microelectronic component.

Example 6 includes the subject matter of any of Examples 1-5, and further specifies that the trench extends into a substrate of the microelectronic component.

Example 7 includes the subject matter of Example 6, and further specifies that the substrate includes a semiconductor material.

Example 8 includes the subject matter of Example 7, and further specifies that the semiconductor material includes silicon.

Example 9 includes the subject matter of any of Examples 1-8, and further specifies that the burr is at an edge of the trench.

Example 10 includes the subject matter of any of Examples 1-9, and further specifies that the burr has a height greater than 300 nanometers.

Example 11 includes the subject matter of any of Examples 1-10, and further specifies that the burr includes material of a substrate of the microelectronic component.

Example 12 includes the subject matter of any of Examples 1-11, and further specifies that the microelectronic component includes a substrate, and side surfaces of the substrate are convex, concave, or angled.

Example 13 includes the subject matter of any of Examples 1-11, and further specifies that the microelectronic component includes a substrate, and side surfaces of the substrate are jagged.

Example 14 includes the subject matter of any of Examples 1-13, and further specifies that corners of the microelectronic component are rounded.

Example 15 includes the subject matter of any of Examples 1-14, and further specifies that a pitch of the conductive contacts is less than 20 microns.

Example 16 includes the subject matter of any of Examples 1-15, and further specifies that the conductive contacts include copper.

Example 17 includes the subject matter of Example 16, and further specifies that the conductive contacts also include manganese and nickel.

Example 18 includes the subject matter of any of Examples 1-17, and further specifies that the conductive contacts include manganese, titanium, gold, silver, palladium, nickel, aluminum, tantalum, or cobalt.

Example 19 includes the subject matter of Example 18, and further specifies that the conductive contacts include tantalum and nitrogen.

Example 20 includes the subject matter of any of Examples 18-19, and further specifies that the conductive contacts include cobalt and iron.

Example 21 includes the subject matter of any of Examples 1-20, and further specifies that the conductive contacts include a bulk metal region and an interface metal region, and a material composition of the interface metal region is different from a material composition of the bulk metal region.

Example 22 includes the subject matter of any of Examples 1-21, and further specifies that the surface includes a direct bonding interface and the conductive contacts are direct bonding contacts.

Example 23 includes the subject matter of Example 22, and further specifies that the direct bonding interface has a root-mean-square surface roughness that is less than Example 0.5 microns.

Example 24 includes the subject matter of any of Examples 22-23, and further specifies that the direct bonding interface includes a dielectric material between adjacent ones of the conductive contacts.

Example 25 includes the subject matter of Example 24, and further specifies that the trench extends through the dielectric material.

Example 26 includes the subject matter of any of Examples 24-25, and further specifies that the direct bonding interface includes a liner material between the conductive contacts and the dielectric material.

Example 27 includes the subject matter of Example 26, and further specifies that the liner material includes silicon and nitrogen.

Example 28 includes the subject matter of any of Examples 26-27, and further specifies that the microelectronic component includes the liner material in a metallization stack.

Example 29 includes the subject matter of any of Examples 25-28, and further specifies that the dielectric material includes an inorganic dielectric material.

Example 30 includes the subject matter of Example 29, and further specifies that the inorganic dielectric material includes silicon and oxygen; silicon and nitrogen; silicon, oxygen, and nitrogen; silicon, carbon, and nitrogen; or silicon, oxygen, carbon, and nitrogen.

Example 31 includes the subject matter of any of Examples 29-30, and further specifies that the dielectric material includes multiple inorganic dielectric materials.

Example 32 includes the subject matter of Example 31, and further specifies that the dielectric material includes a first inorganic dielectric material and a second inorganic dielectric material different from the first inorganic dielectric material.

Example 33 includes the subject matter of Example 32, and further specifies that the first inorganic dielectric material includes silicon and oxygen, and the second inorganic dielectric material includes silicon, oxygen, carbon, and nitrogen.

Example 34 includes the subject matter of any of Examples 32-33, and further specifies that the dielectric material includes more of the first inorganic dielectric material than the second inorganic dielectric material.

Example 35 includes the subject matter of any of Examples 1-34, and further specifies that the microelectronic component is a die.

Example 36 includes the subject matter of any of Examples 1-34, and further specifies that the microelectronic component is an interposer.

Example 37 includes the subject matter of any of Examples 1-36, and further specifies that the microelectronic component includes a through-substrate via.

Example 38 includes the subject matter of any of Examples 1-37, and further specifies that the microelectronic component does not include transistors or diodes.

Example 39 includes the subject matter of any of Examples 1-37, and further specifies that the microelectronic component includes active circuitry.

Example 40 includes the subject matter of Example 39, and further specifies that the active circuitry includes memory circuitry or power delivery circuitry.

Example 41 includes the subject matter of any of Examples 1-40, and further specifies that the surface is a first surface, the conductive contacts are first conductive contacts, the microelectronic component includes a second surface opposite to the first surface, and second conductive contacts are at the second surface.

Example 42 is a microelectronic assembly, including: a first microelectronic component having a face having a first direct bonding interface, wherein the first microelectronic component has a trench at a perimeter of the face; and a second microelectronic component having a second direct bonding interface, wherein the first direct bonding interface is direct bonded to the second direct bonding interface.

Example 43 includes the subject matter of Example 42, and further specifies that the trench has a depth greater than 1 micron.

Example 44 includes the subject matter of any of Examples 42-43, and further specifies that the trench has a depth between 2 microns and 25 microns.

Example 45 includes the subject matter of any of Examples 42-44, and further specifies that the trench has a width that is greater than 2 microns.

Example 46 includes the subject matter of any of Examples 42-45, and further specifies that the trench extends into a metallization stack of the first microelectronic component.

Example 47 includes the subject matter of any of Examples 42-46, and further specifies that the trench extends into a substrate of the first microelectronic component.

Example 48 includes the subject matter of Example 47, and further specifies that the substrate includes a semiconductor material.

Example 49 includes the subject matter of Example 48, and further specifies that the semiconductor material includes silicon.

Example 50 includes the subject matter of any of Examples 42-49, and further specifies that the first microelectronic component includes a burr in the trench.

Example 51 includes the subject matter of Example 50, and further specifies that the burr is at an edge of the trench.

Example 52 includes the subject matter of any of Examples 50-51, and further specifies that the burr has a height greater than 300 nanometers.

Example 53 includes the subject matter of any of Examples 50-52, and further specifies that the burr includes material of a substrate of the first microelectronic component.

Example 54 includes the subject matter of any of Examples 42-53, and further specifies that the first microelectronic component includes a substrate, and side surfaces of the substrate are convex, concave, or angled.

Example 55 includes the subject matter of any of Examples 42-53, and further specifies that the first microelectronic component includes a substrate, and side surfaces of the substrate are jagged.

Example 56 includes the subject matter of any of Examples 42-55, and further specifies that corners of the first microelectronic component are rounded.

Example 57 includes the subject matter of any of Examples 42-56, and further specifies that the first direct bonding interface includes conductive contacts.

Example 58 includes the subject matter of Example 57, and further specifies that a pitch of the conductive contacts is less than 20 microns.

Example 59 includes the subject matter of any of Examples 57-58, and further specifies that the conductive contacts include copper.

Example 60 includes the subject matter of Example 59, and further specifies that the conductive contacts also include manganese and nickel.

Example 61 includes the subject matter of any of Examples 57-60, and further specifies that the conductive contacts include manganese, titanium, gold, silver, palladium, nickel, aluminum, tantalum, or cobalt.

Example 62 includes the subject matter of Example 61, and further specifies that the conductive contacts include tantalum and nitrogen.

Example 63 includes the subject matter of any of Examples 61-62, and further specifies that the conductive contacts include cobalt and iron.

Example 64 includes the subject matter of any of Examples 57-63, and further specifies that the conductive contacts include a bulk metal region and an interface metal region, and a material composition of the interface metal region is different from a material composition of the bulk metal region.

Example 65 includes the subject matter of any of Examples 57-64, and further specifies that the first direct bonding interface includes a dielectric material between adjacent ones of the conductive contacts.

Example 66 includes the subject matter of Example 65, and further specifies that the trench extends through the dielectric material.

Example 67 includes the subject matter of any of Examples 65-66, and further specifies that the first direct bonding interface includes a liner material between the conductive contacts and the dielectric material.

Example 68 includes the subject matter of Example 67, and further specifies that the liner material includes silicon and nitrogen.

Example 69 includes the subject matter of any of Examples 67-68, and further specifies that the first microelectronic component includes the liner material in a metallization stack.

Example 70 includes the subject matter of any of Examples 65-69, and further specifies that the dielectric material includes an inorganic dielectric material.

Example 71 includes the subject matter of Example 70, and further specifies that the inorganic dielectric material includes silicon and oxygen; silicon and nitrogen; silicon, oxygen, and nitrogen; silicon, carbon, and nitrogen; or silicon, oxygen, carbon, and nitrogen.

Example 72 includes the subject matter of any of Examples 70-71, and further specifies that the dielectric material includes multiple inorganic dielectric materials.

Example 73 includes the subject matter of Example 72, and further specifies that the dielectric material includes a first inorganic dielectric material and a second inorganic dielectric material different from the first inorganic dielectric material.

Example 74 includes the subject matter of Example 73, and further specifies that the first inorganic dielectric material includes silicon and oxygen, and the second inorganic dielectric material includes silicon, oxygen, carbon, and nitrogen.

Example 75 includes the subject matter of any of Examples 73-74, and further specifies that the dielectric material includes more of the first inorganic dielectric material than the second inorganic dielectric material.

Example 76 includes the subject matter of any of Examples 42-75, and further specifies that the first direct bonding interface has a root-mean-square surface roughness that is less than Example 0.5 microns.

Example 77 includes the subject matter of any of Examples 42-76, and further specifies that the first microelectronic component is a die.

Example 78 includes the subject matter of any of Examples 42-76, and further specifies that the first microelectronic component is an interposer.

Example 79 includes the subject matter of any of Examples 42-78, and further specifies that the first microelectronic component includes a through-substrate via.

Example 80 includes the subject matter of any of Examples 42-79, and further specifies that the first microelectronic component does not include transistors or diodes.

Example 81 includes the subject matter of any of Examples 42-79, and further specifies that the first microelectronic component includes active circuitry.

Example 82 includes the subject matter of Example 81, and further specifies that the active circuitry includes memory circuitry or power delivery circuitry.

Example 83 includes the subject matter of any of Examples 42-82, and further specifies that the face is a first face, the first microelectronic component includes a second face opposite to the first face, and conductive contacts are at the second face.

Example 84 includes the subject matter of any of Examples 42-83, and further specifies that the face is a first face, the trench is a first trench, the second direct bonding interface is at a second face of the second microelectronic component, and the second microelectronic component has a second trench at a perimeter of the second face.

Example 85 includes the subject matter of Example 84, and further specifies that the second trench has a depth greater than 1 micron.

Example 86 includes the subject matter of any of Examples 84-85, and further specifies that the second trench has a depth between 2 microns and 25 microns.

Example 87 includes the subject matter of any of Examples 84-86, and further specifies that the second trench has a width that is greater than 2 microns.

Example 88 includes the subject matter of any of Examples 84-87, and further specifies that the second trench extends into a metallization stack of the second microelectronic component.

Example 89 includes the subject matter of any of Examples 84-88, and further specifies that the second trench extends into a substrate of the second microelectronic component.

Example 90 includes the subject matter of Example 89, and further specifies that the substrate includes a semiconductor material.

Example 91 includes the subject matter of Example 90, and further specifies that the semiconductor material includes silicon.

Example 92 includes the subject matter of any of Examples 84-91, and further specifies that the second microelectronic component includes a burr in the second trench.

Example 93 includes the subject matter of Example 92, and further specifies that the burr is at an edge of the second trench.

Example 94 includes the subject matter of any of Examples 92-93, and further specifies that the burr has a height greater than 300 nanometers.

Example 95 includes the subject matter of any of Examples 92-94, and further specifies that the burr includes material of a substrate of the second microelectronic component.

Example 96 includes the subject matter of any of Examples 84-95, and further specifies that the second microelectronic component includes a substrate, and side surfaces of the substrate are convex, concave, or angled.

Example 97 includes the subject matter of any of Examples 84-95, and further specifies that the second microelectronic component includes a substrate, and side surfaces of the substrate are jagged.

Example 98 includes the subject matter of any of Examples 84-97, and further specifies that corners of the second microelectronic component are rounded.

Example 99 includes the subject matter of any of Examples 84-98, and further specifies that the second direct bonding interface includes conductive contacts.

Example 100 includes the subject matter of Example 99, and further specifies that a pitch of the conductive contacts is less than 20 microns.

Example 101 includes the subject matter of any of Examples 99-100, and further specifies that the conductive contacts include copper.

Example 102 includes the subject matter of Example 101, and further specifies that the conductive contacts also include manganese and nickel.

Example 103 includes the subject matter of any of Examples 99-102, and further specifies that the conductive contacts include manganese, titanium, gold, silver, palladium, nickel, aluminum, tantalum, or cobalt.

Example 104 includes the subject matter of Example 103, and further specifies that the conductive contacts include tantalum and nitrogen.

Example 105 includes the subject matter of any of Examples 103-104, and further specifies that the conductive contacts include cobalt and iron.

Example 106 includes the subject matter of any of Examples 99-105, and further specifies that the conductive contacts include a bulk metal region and an interface metal region, and a material composition of the interface metal region is different from a material composition of the bulk metal region.

Example 107 includes the subject matter of any of Examples 99-106, and further specifies that the second direct bonding interface includes a dielectric material between adjacent ones of the conductive contacts.

Example 108 includes the subject matter of Example 107, and further specifies that the second trench extends through the dielectric material.

Example 109 includes the subject matter of any of Examples 107-108, and further specifies that the second direct bonding interface includes a liner material between the conductive contacts and the dielectric material.

Example 110 includes the subject matter of Example 109, and further specifies that the liner material includes silicon and nitrogen.

Example 111 includes the subject matter of any of Examples 109-110, and further specifies that the second microelectronic component includes the liner material in a metallization stack.

Example 112 includes the subject matter of any of Examples 107-111, and further specifies that the dielectric material includes an inorganic dielectric material.

Example 113 includes the subject matter of Example 112, and further specifies that the inorganic dielectric material includes silicon and oxygen; silicon and nitrogen; silicon, oxygen, and nitrogen; silicon, carbon, and nitrogen; or silicon, oxygen, carbon, and nitrogen.

Example 114 includes the subject matter of any of Examples 112-113, and further specifies that the dielectric material includes multiple inorganic dielectric materials.

Example 115 includes the subject matter of Example 114, and further specifies that the dielectric material includes a first inorganic dielectric material and a second inorganic dielectric material different from the first inorganic dielectric material.

Example 116 includes the subject matter of Example 115, and further specifies that the first inorganic dielectric material includes silicon and oxygen, and the second inorganic dielectric material includes silicon, oxygen, carbon, and nitrogen.

Example 117 includes the subject matter of any of Examples 115-116, and further specifies that the dielectric material includes more of the first inorganic dielectric material than the second inorganic dielectric material.

Example 118 includes the subject matter of any of Examples 84-117, and further specifies that the second direct bonding interface has a root-mean-square surface roughness that is less than Example 0.5 microns.

Example 119 includes the subject matter of any of Examples 84-118, and further specifies that the second microelectronic component is a die.

Example 120 includes the subject matter of any of Examples 84-118, and further specifies that the second microelectronic component is an interposer.

Example 121 includes the subject matter of any of Examples 84-120, and further specifies that the second microelectronic component includes a through-substrate via.

Example 122 includes the subject matter of any of Examples 84-121, and further specifies that the second microelectronic component does not include transistors or diodes.

Example 123 includes the subject matter of any of Examples 84-121, and further specifies that the second microelectronic component includes active circuitry.

Example 124 includes the subject matter of any of Examples 123, and further specifies that the active circuitry includes memory circuitry or power delivery circuitry.

Example 125 includes the subject matter of any of Examples 42-124, and further specifies that the microelectronic assembly further includes a mold material around the second microelectronic component.

Example 126 includes the subject matter of Example 125, and further specifies that the mold material does not extend between the second microelectronic component and the first microelectronic component.

Example 127 includes the subject matter of any of Examples 125-126, and further specifies that the mold material includes a glass material or an oxide material or a filler material.

Example 128 includes the subject matter of any of Examples 42-127, and further specifies that the microelectronic assembly further includes a heat spreader.

Example 129 includes the subject matter of Example 128, and further specifies that the microelectronic assembly further includes a thermal interface material between the second microelectronic component and the heat spreader.

Example 130 is a system, including: a circuit board; and a microelectronic assembly, communicatively coupled to the circuit board, wherein the microelectronic assembly includes a face of a first microelectronic component direct bonded to a face of a second microelectronic component, and the face of the first microelectronic component includes a trench at its edges.

Example 131 includes the subject matter of Example 130, and further specifies that the circuit board is a motherboard.

Example 132 includes the subject matter of any of Examples 130-131, and further specifies that the system is a handheld computing system.

Example 133 includes the subject matter of any of Examples 130-132, and further specifies that the system is a wearable computing system.

Example 134 includes the subject matter of any of Examples 130-131, and further specifies that the system is a server computing system.

Example 135 includes the subject matter of any of Examples 130-131, and further specifies that the system is a vehicular computing system.

Example 136 includes the subject matter of any of Examples 130-135, and further specifies that the system further includes a display communicatively coupled to the circuit board.

Example 137 includes the subject matter of any of Examples 130-136, and further specifies that the system further includes a wireless communication device communicatively coupled to the circuit board.

Example 138 includes the subject matter of any of Examples 130-137, and further specifies that the system further includes a housing around the microelectronic assembly and the circuit board. 

1. A microelectronic component, comprising: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.
 2. The microelectronic component of claim 1, wherein the trench extends into a metallization stack of the microelectronic component.
 3. The microelectronic component of claim 1, wherein the trench extends into a substrate of the microelectronic component.
 4. The microelectronic component of claim 3, wherein the substrate includes a semiconductor material.
 5. The microelectronic component of claim 1, wherein the burr is at an edge of the trench.
 6. The microelectronic component of claim 1, wherein the burr has a height greater than 300 nanometers.
 7. The microelectronic component of claim 1, wherein the burr includes material of a substrate of the microelectronic component.
 8. The microelectronic component of claim 1, wherein the microelectronic component includes a substrate, and side surfaces of the substrate are convex, concave, or angled.
 9. The microelectronic component of claim 1, wherein the microelectronic component includes a substrate, and side surfaces of the substrate are jagged.
 10. The microelectronic component of claim 1, wherein corners of the microelectronic component are rounded.
 11. A microelectronic assembly, comprising: a first microelectronic component having a face having a first direct bonding interface, wherein the first microelectronic component has a trench at a perimeter of the face; and a second microelectronic component having a second direct bonding interface, wherein the first direct bonding interface is direct bonded to the second direct bonding interface.
 12. The microelectronic assembly of claim 11, wherein the first direct bonding interface includes conductive contacts.
 13. The microelectronic assembly of claim 12, wherein a pitch of the conductive contacts is less than 20 microns.
 14. The microelectronic assembly of claim 12, wherein the conductive contacts include copper.
 15. The microelectronic assembly of claim 12, wherein the first direct bonding interface includes a dielectric material between adjacent ones of the conductive contacts.
 16. The microelectronic assembly of claim 15, wherein the dielectric material includes an inorganic dielectric material.
 17. The microelectronic assembly of claim 11, wherein the face is a first face, the trench is a first trench, the second direct bonding interface is at a second face of the second microelectronic component, and the second microelectronic component has a second trench at a perimeter of the second face.
 18. The microelectronic assembly of claim 17, wherein the second microelectronic component includes a burr in the second trench.
 19. A system, comprising: a circuit board; and a microelectronic assembly, communicatively coupled to the circuit board, wherein the microelectronic assembly includes a face of a first microelectronic component direct bonded to a face of a second microelectronic component, and the face of the first microelectronic component includes a trench at its edges.
 20. The system of claim 19, wherein the system further includes a display communicatively coupled to the circuit board. 